Power saving is a primary goal of electronics designers. For electronic apparatuses, such as laptop computers, power consumption is an essential factor of their performance. A laptop computer's display and graphics card may consume nearly half of the total power consumption of the device. Accordingly, developing energy-efficient display devices is an ongoing focus area for mobile personal computer manufacturers. For example, thin film transistor (TFT) liquid crystal display (LCD) devices have active pixel transistors that store charge at a switch rate proportional to the display refresh rate. In addition, a prior art graphics controller displays interface signals at a rate proportional to the display refresh rate. In other words, the operational rate of the prior art graphics controller may be varied with the display refresh rate of the display device. When the display refresh rate of the display device is predetermined, whether the graphics controller needs to output signals or not, the graphics controller has to work at the rate proportional to the predetermined display refresh rate. Therefore, even when there are identical display signals, the graphics controller has to work at a high rate, which results in low efficiency and high power-consumption.
An electronic apparatus, such as a laptop computer, usually uses a timing controller for receiving display and control signals from a graphics controller of the electronic apparatus, and converts the received signals into display signals for an associated LCD device.
Referring to PRIOR ART FIG. 1, a prior art timing controller 100 is illustrated. A Low Voltage Differential Signaling (LVDS) based Flat Panel Display (FPD) Link receiver 102 receives data signals and control signals. The received signals are a part of a parallel data stream which is routed to an 8-6 bit translator 104 for matching color depth. Through shifting the data length, the color depth is modified by the translator 104. The data path and timing REF 106 is coupled to the 8-6 bit translator 104 for separating the data signals to a serializer 108 and the control signals to a vertical and horizontal timing generation 112. The data signals are converted and serialized by the data path and timing REF 106 and serializer 108 into Reduced Swing Differential Signaling (RSDS) which needs timing adjustment, and outputted by the RSDS TX 110. The control signals generated by the vertical and horizontal timing generation 112 are sent to source drivers, gate drivers and power supply.
Another timing controller may combine frame memory for Response Time Compensation (RTC) in the prior art. The RTC feature is implemented by means of using a boost or overdrive voltage that forces the liquid crystal material to respond more rapidly. This boost or overdrive is accomplished by combination of an internal or external Electrically Erasable Programmable Read-Only Memory (EEPROM) Look up Table (LUT), which contains the boost/overdrive levels and external memory that acts as a frame buffer. The RTC improves the intra-gray level response time of the LCD panel. This design uses frame memory for RTC but not for power saving.
Typically, a graphics controller in the prior art converts a set of source images or surfaces, combines them and sends them out at the proper timing to an output interface connected to a display device. Along the way, the data can be converted from one format to another, stretched or shrunk, and color-corrected or gamma-converted.
The graphics controller comprises display engines, display planes, a display data channel, and so on. Display engines, comprise video engine, two-direction (2D) engine, and three-direction (3D) engine, which fetches display data from system memory. The display planes of the graphics controller comprise rectangular-shaped images that have characteristics including source, size, position, method, and format. These planes are associated with a particular destination pipe, and the pipe is associated with ports. The Display Data Channel (DDC) allows communication between the host system and display. Both configuration and control information can be exchanged allowing plug-and-play systems to be realized.
The display data of the graphics controller is converted into LVDS signals or signals which is serialized data received by a timing controller. The output signals comply with a standard established by the TIA/EIA (Telecommunications Industry Association/Electronic Industries Association) ANSI/TIA/EIA-644-A (LVDS), which are sent to a LCD device through a timing controller.